Beam Trip Analysis by Bunch-by-bunch BPM System in BEPCII

A new bunch-by-bunch beam position measurement (BPM) prototype has been designed and built to monitor the beam instability and analyse the beam trip in the BEPCII (Beijing Electron-Positron ColliderII) machine. The broadband electronics system which employs fast analogy digital converter (ADC) and field programmable gate array (FPGA) can obtain the beam information bunch-by-bunch with high bunch-to-bunch isolation. Therefore, the system can analyse the beam motion bunch-by-bunch both in time domain and in frequency domain. In this paper we will present the system architecture and discuss some beam trip analysis result, such as RF trip, beam instabilities and magnet power instabilities. INTRODUCTION The performance of storage ring accelerator can be greatly degraded due to beam trip as the result of various subsystem failure. For the collider, the beam trip can significantly reduce the integer luminance. Analysing the causes of beam trip by post-mortem diagnose system can help us to improve the reliability of subsystem and reduce troubleshooting effort [1]-[3]. Bunch-by-bunch measurement is widely used in feedback system for control of coupled-bunch instabilities in circular accelerators. In practice, bunch-by-bunch data can be used to analyse the beam instabilities and beam trip events [4]. A bunch-by-bunch BPM system has been developed to measurement beam position bunch-bybunch, and it is effectually to analyse the beam trip events. BEPCII is an electron-positron double-ring collider which is designed to operate at about 1A beam current. Some major deigned parameters related to the beam trip analysis are listed in table1. BUNCH-BY-BUNCH SYSTEM Typically, the system consists of the front-end, the digital signal processor board which contain ADCs and FPGA and the upper control computer. The important point has to be made before we delve into the details of the front end. Based on the NyquistShannon sampling theorem, it’s expect that the input signal to be band-limited within the half of sampling rate to prevent aliasing. The bunch-by-bunch measurement system operates at a sampling rate of RF frequency, and the aliasing is used to achieve high isolation between neighbouring samples. The system analogue bandwidth is larger than the first Nyquist band and all elements of the front end should have large analogue bandwidth to prevent the bunch to bunch coupling [5]. Front-end and ADC Sampling The schematic of the front-end is sketched in fig.1. The four channel analogue signals are normally generated by pickup with 50Ohm termination. The attenuators adjust the amplitude of the analogue signal. As the four cables are not in the same length, the phase shifters adjust the signal phase in accordance with each other. Figure 1: Layout of front-end. The digital signal processor board has four 14 bits resolution ADCs which work at the sampling rate of 499.8MHz. As the ADC analogue bandwidth is form DC to 800MHz, it means that the pulse width of analogue signal is broaden by pass the 800MHz low pass filter, and it can’t achieve completely isolation between neighbouring samples with 499.8MHz sampling rate. However, for BEPCII injection pattern, the minimum bunch interval in is 4 ns, and it can achieve high isolation for each bunch. low pass filter phase shifter attenuator A A D A D A D A D Phase shifter Sampling clock To FPGA B